Sensing apparatus and data sensing method thereof

ABSTRACT

A sensing apparatus and data sensing method are provided. The sensing apparatus includes an initial circuit, a reference current generator and a sensing circuit. The initial circuit discharges a sensing end to a reference ground during a discharge period, and pre-charges the sensing end to a preset voltage level during a pre-charge period according to an output signal. The reference current generator draws a reference current from the sensing end. The sensing circuit senses a voltage level on the sensing end to generate the output signal. Wherein, the sensing end receives a cell current from a memory cell, and the pre-charge period is after the discharge period.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention generally relates to a sense amplifier and a datasensing method thereof, and more particularly to a sense amplifier andsensing method for reducing the data sensing time.

2. Description of Prior Art

Along with the rapid development of the semiconductor process technique,a voltage level of an operating voltage for an integrated circuit isgetting lower. For non-volatile memory cell, a current level of a cellcurrent flowing to a sense amplifier is small when the voltage level ofthe operating voltage is low (ex. VDD=1.5V/1.2V or 1.0V). When data inthe non-volatile memory cell is sensed by a sense amplifier, a long timeis needed for the current of the cell to charge a bit line. That is, adata sensing time for a voltage level on a sensing end to rise to largerthan a trigger level is long, and the performance of the non-volatilememory cell is limited.

SUMMARY OF THE INVENTION

The present invention provides a sensing apparatus for reducing thesensing time for sensing data from memory cell.

The present invention provides a data sensing method for reducing thesensing time for sensing data from memory cell

The sensing apparatus provided by the present invention includes aninitial circuit, a reference current generator and a sensing circuit.The initial circuit is coupled to a sensing end. The initial circuitdischarges the sensing end to a reference ground during a dischargeperiod, and pre-charges the sensing end to a preset voltage level duringa pre-charge period according to an output signal. The reference currentgenerator is coupled to the sensing end and draws a reference currentfrom the sensing end. The sensing circuit is coupled to the sensing endfor sensing a voltage level on the sensing end to generate the outputsignal. Wherein, the sensing end receives a cell current from a memorycell, and the pre-charge period is after the discharge period.

The steps of the data sensing method provided by the present inventionincludes: discharging a voltage level on a sensing end to a referenceground during a discharge period by an initial circuit; pre-charging thevoltage level on the sensing end to a preset voltage level during apre-charge period according to an output signal by the initial circuit;receiving a cell current from the memory cell by the sensing end;drawing a reference current from the sensing end by a reference currentgenerator; and generating the output signal by sensing the voltage levelon the sensing end by a sensing circuit. Wherein, the pre-charge periodis after the discharge period.

Accordingly, the sensing apparatus provided by present invention pullsup the voltage level on the sensing end to the preset voltage levelduring the pre-charge period. That is, when the pre-charge period isfinished, the voltage level can be raised to larger than the triggervoltage level quickly, and the necessary sensing time for the sensingapparatus can be reduced.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a block diagram of a sensing apparatus 100 according to anembodiment of the present invention.

FIG. 2 is a block diagram of the initial circuit 110 according to theembodiment of the present invention.

FIG. 3A is a circuit diagram of a sensing apparatus 300 according toanother embodiment of the present invention.

FIG. 3B is a circuit diagram of the pre-charge circuit 311 according toanother embodiment of the sensing apparatus 300.

FIG. 4 is a waveform plot according to the embodiment of the presentinvention.

FIG. 5 is a flow chart of a data sensing method according to anembodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferred embodimentof the invention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

Referring to FIG. 1, FIG. 1 is a block diagram of a sensing apparatus100 according to an embodiment of the present invention. The sensingapparatus 100 includes an initial circuit 110, a reference currentgenerator 120, and a sensing circuit 130. The initial circuit 110 iscoupled to a sensing end SE, and the sensing end SE further coupled to amemory cell 170. The memory cell 170 may be one of the cells of anon-volatile memory. The initial circuit 110 receives a pre-chargeenable signal PREEN and a discharge enable signal DISEN, and the initialcircuit 110 also receives an output signal OUT feedback from the sensingcircuit 130. The initial circuit 110 may discharge the sensing end SE toa reference ground according to the discharge enable signal DISEN, orthe initial circuit 110 may pre-charge the sensing end SE to a presetvoltage level according to the pre-charge enable signal PREEN and theoutput signal OUT. In the embodiment, the pre-charge enable signal PREENis used to indicate whether the sensing apparatus 100 is in a pre-chargeperiod or not, and the discharge enable signal DISEN is used to indicatewhether the sensing apparatus 100 is in a discharge period or not.Moreover, the discharge period is before the pre-charge period.

The reference current generator 120 is coupled to the sensing end SE.The reference current generator 120 generates a reference current IREF,and the reference current generator 120 draws the reference current IREFfrom the sensing end SE to the reference round. In the embodiment, thememory cell 170 provides a cell current ICELL to the sensing end SE, andthe reference current generator 120 draws the reference current IREFfrom the sensing end SE. Such as that, a current comparing operation isoperated on the sensing end SE. When the cell current ICELL is higherthan the reference current IREF, a voltage level on the sensing end SEis raised. On the contrary, when the cell current ICELL is lower thanthe reference current IREF, the voltage level on the sensing end SE isreduced. Moreover, when the cell current ICELL equals to the referencecurrent IREF, the voltage level on the sensing end SE is not varied.

On the other hand, the reference current generator 120 receives aninverted pre-charge enable signal ZPREEN. The reference currentgenerator 120 decides whether to generate the reference current IREF ornot according to the inverted pre-charge enable signal ZPREEN, and theinverted pre-charge enable signal ZPREEN and the pre-charge enablesignal PREEN are complementary. That is, the reference current IREF isnot generated during the pre-charge period.

The sensing circuit 130 is coupled to the sensing end SE. The sensingcircuit 130 senses the voltage level on the sensing end SE to generatethe output signal OUT. For example, the sensing circuit 130 may detectwhether the voltage level on the sensing end SE is higher than a triggervoltage level or not for generating the output signal. In detail, whenthe voltage level on the sensing end SE is higher than the triggervoltage level, the sensing circuit 130 may determine the output signalto be a first logic state. On the contrary, when the voltage level onthe sensing end SE is not higher than the trigger voltage level, thesensing circuit 130 may determine the output signal to be a second logicstate. The sensing circuit 130 further receives the pre-charge enablesignal PREEN, and the sensing circuit 130 may provide a current drawingfrom an output end of the sensing circuit 130 to the reference groundduring the pre-charge period. The current provided by the sensingcircuit 130 can the output signal OUT from overshooting.

It should be noted here, the trigger voltage level is larger the presetvoltage level. The preset voltage level may be determined by a designeraccording to the trigger voltage level.

In the operation of the sensing apparatus 100, firstly, in the dischargeperiod, the initial circuit 110 discharges the sensing end SE to thereference ground (ex. 0V). Then, after the discharge period and in thepre-charge period, the initial circuit 110 pre-charges the sensing endSE to the preset voltage level. After the pre-charge period, thereference current generator 120 provides the reference current IREFdrawing from the sensing end SE. When the memory cell 170 is accessed,the memory cell 170 provides the cell current ICELL to the sensing endSE, and the voltage level on the sensing end SE is varied by comparingthe cell current ICELL and the reference current IREF. If the cellcurrent ICELL is larger than the reference current IREF, the voltagelevel on the sensing end SE may increase to larger than the triggervoltage level from the preset voltage level quickly, and the sensingcircuit 130 can generates the output signal OUT quickly by sensing thevoltage level on the sensing end SE.

On the other hand, if the cell current ICELL is not larger than thereference current IREF, the voltage level on the sensing end SE reducedfrom the preset voltage level to the reference ground. The sensingcircuit 130 can generates the output signal OUT quickly by sensing thevoltage level on the sensing end SE.

Referring to FIG. 2, FIG. 2 is a block diagram of the initial circuit110 according to the embodiment of the present invention. The initialcircuit 110 includes a pre-charge circuit 111 and a discharge circuit112. The pre-charge circuit 111 is coupled to the reference operatingvoltage Vdd and the sensing end SE. The pre-charge circuit 111 receivesthe pre-charge enable signal PREEN and the output signal OUT, and thepre-charge circuit 111 pre-charges the sensing end SE to the presetvoltage level according to the output signal OUT during the pre-chargeperiod.

The discharge circuit 112 is coupled to the reference ground GND and thesensing end SE. The discharge circuit 112 receives the discharge enablesignal DISEN, and discharge the sensing end SE to the reference groundGND during the discharge period.

Referring to FIG. 3A, FIG. 3A is a circuit diagram of a sensingapparatus 300 according to another embodiment of the present invention.The sensing apparatus 300 is coupled to the memory cell 370 for readinga data stored in the memory cell 370. The sensing apparatus 300 includesan initial circuit 310, a reference current generator 320, a sensingcircuit 330, a latch circuit 340 and a switch SW1.

The switch SW1 is coupled between a sensing end SE and the memory cell370. The switch SW1 is controlled by a sense amplifier enable signalENSA and an inverted sense amplifier enable signal ZENSA. In thisembodiment, the switch SW1 includes a transmission gate. A first andsecond ends of the transmission gate are respectively coupled to thememory cell 370 and the sensing end SE. A positive and negative controlends of the transmission gate are respectively receive the sensingapparatus enable signal ENSA and the inverted sensing apparatus enablesignal ZENSA. The sensing apparatus enable signal ENSA and the invertedsensing apparatus enable signal ZENSA are complementary. When a datastored in the memory cell 370 is read, the switch SW1 is turned onaccording to the sensing apparatus enable signal ENSA and the invertedsensing apparatus enable signal ZENSA, and when the memory cell 370 isnot accessed, the switch SW1 is turned off.

The transmission gate of the switch SW1 is formed by transistors MP1 andMN9. The transistor MP1 is P-type MOSFET, and the transistor MN9 isN-type MOSFET.

The initial circuit 310 includes a pre-charge circuit 311 and adischarge circuit 312. The pre-charge circuit 311 includes transistorsMN0 and MN1. A first end of the transistor MN0 is coupled to thereference operating voltage VDD, a control end of the transistor MN0receives the pre-charge enable signal PREEN, and a second end of thetransistor MN0 is coupled to a first end of the transistor MN1. Acontrol end of the transistor MN1 is coupled to the sensing circuit 330form receiving the output signal OUT. A second end of the transistor MN1is coupled to the sensing end SE. The discharge circuit 312 includes atransistor MN2. A first end of the transistor MN2 is coupled to thesensing end SE, and a control end of the transistor MN2 receives adischarge enable signal DISEN, and a second end of the transistor MN2 iscoupled to a reference ground GND. Beside, the transistors MN0-MN2 areN-type transistors.

The reference current generator 320 includes a transistor MN3 and atransistor MN4. A first end of the transistor MN3 is coupled to thesensing end SE, a control end of the transistor MN3 receives a referencevoltage VREF, and a second end of the transistor MN3 is coupled to afirst end of the transistor MN4. A control end of the transistor MN4receives an inverted pre-charge enable signal ZPREEN, and a second endof the transistor MN4 is coupled to the reference ground GND.

The transistor MN4 performs a switch, and controlled by the invertedpre-charge enable signal ZPREEN. The transistor MN4 coupled thetransistor MN3 to the reference ground GND when the sensing apparatus300 is not in the pre-charge period. The transistor MN3 performs acurrent source, and provides the reference current IREF according to thereference voltage VREF when the transistor MN4 is turned on.

The sensing circuit 330 includes transistors MP0, a current generator(MN5 and MN6) and an overshoot prevention circuit 331. The transistorsMP0, MN5 and MN6 form a circuit for sensing the voltage level VSA on thesensing end SE. A first end of the transistor MP0 is coupled to thereference operating voltage VDD, a control end of the transistor MP0 iscoupled to the sensing end SE, and a second end of the transistor MP0 isan output end of the sensing circuit 330, and the output end of thesensing circuit 330 is coupled to a first end of the transistor MN5.Further, a control end of the transistor MN5 receives a bias voltageNBIAS, and a second end of the transistor MN5 is coupled to a first endof the transistor MN6. A control end of the transistor MN6 receives thesense amplifier enable signal ENSA, and a second end of the transistorMN6 is coupled to the reference ground GND.

The overshoot prevention circuit 331 is coupled between the output endof the sensing circuit 330 and the reference ground GND. The overshootprevention circuit 331 includes transistors MN7 and MN8. The transistorMN7 is coupled between the transistor MN8 and the output end of thesensing circuit 330, and the transistor MN7 is controlled by the biasvoltage NBIAS to perform a current source. The transistor MN8 performs aswitch, and coupled between the transistor MN7 and the reference ground.The transistor is controlled by the pre-charge enable signal PREEN, andis turned on during the pre-charge period.

The overshoot prevention circuit 331 provides a current generated by thetransistor MN7 during the pre-charge period to prevent the output signalOUT from overshooting. A data sensing fault event during the pre-chargeperiod can be avoided.

The latch circuit 340 is coupled to the sensing circuit 330 to receivethe output signal OUT. The latch circuit 340 latches the output signalOUT according a latch signal ENLAT. The latch signal ENLAT may be enableafter the pre-charge period. In this embodiment, the latch circuit 340includes a logic gate (NOR gate) 341 and a latch gate 342. The logicgate 341 receives the output signal OUT and an inverted latch enablesignal ZENLAT, and the logic gate 341 decides to transmit the outputsignal OUT to an output end of the logical gate 341 or not according tothe inverted latch signal ZENLAT. In this embodiment, the output signalOUT is inverted and the inverted output signal is transported to theoutput end of the logical gate 341 when the inverted latch enable signalZENLAT is logic low.

The latch gate 342 has a data end, an enable end, and an output end. Thedata end D of the latch gate 342 is coupled to the output end of thelogical gate 341, the enable end E of the latch gate 342 receives thelatch enable signal ENLAT, and the output end Q of the latch gate 342outputs a latched output signal LATOUT.

Referring to FIG. 3B, FIG. 3B is a circuit diagram of the pre-chargecircuit 311 according to another embodiment of the sensing apparatus300. In FIG. 3B, the pre-charge circuit 311 includes a current sourceIR1, a switch SW1, and a transistor MN1. The current source IR1 iscoupled to the reference operating voltage VDD and generates a referencecurrent. The reference current is provided to the switch SW1. The twoends of the switch SW1 are respectively coupled to the current sourceIR1 and the transistor MN1. The switch SW1 is controlled by thepre-charge enable signal PREEN to be turned on or off. When the switchSW1 is turned on according to the pre-charge enable signal PREEN, thereference current generated by the current source IR1 can be provided tothe first end of the transistor MN1. The second end of the transistorMN1 is coupled to the sensing end SE, and the control end of thetransistor MN1 receives the output signal OUT. Different from FIG. 3A,the transistor MN0 is replace to the current source IR1 and switch SW1in FIG. 3B.

Referring to FIG. 3A and FIG. 4, wherein, FIG. 4 is a waveform plotaccording to the embodiment of the present invention. The timing periodTA1 is used for sensing a memory cell which is programmed to a firstlogic level (“0” for example). During the timing period TA1, the memorycell 370 is programmed and is sensed by the sensing apparatus 300.Firstly, during the discharge period TD1, the sense amplifier enablesignal ENSA and the discharge enable signal DISEN are enable (be pulledto logic high), and the voltage level VSA on the sensing end SE ispulled to the reference ground (ex. 0V). Then, during pre-charge periodTP1, the discharge signal DISEN is pulled to logic low, the pre-chargesignal is pulled to logic high, and the voltage level VSA on the sensingend SE is pulled to the preset voltage level VPRE. Wherein, the presetvoltage level VPRE is lower than the trigger voltage level VTRIG. Whenthe pre-charge period TP1 is finished, the voltage level VSA isgradually increased by the comparing result of the cell current ICELLand the reference current IREF. At the time point TLAT, the voltagelevel VSA is not lower than the trigger voltage level VTRIG, and acorrect output signal OUT can be generated. That is, the latch circuit340 can latch the correct output signal OUT at the time point TLAT, andthe correct latched output signal LATOUT can be obtained quickly.

Please referring to the curve C1, if the voltage level VSA is not pulledto the preset voltage level VPRE in the pre-charge period TP1, thecorrect latched output signal LATOUT can be obtained after the timepoint TT. Apparently, the response speed of the sensing apparatus 300 isimproved.

In another case, the timing period TA2 is used for sensing a memory cellwhich is programmed or erased to a second logic level (“1” for example).During the timing period TA2, the memory cell 370 is erased and issensed by the sensing apparatus 300. Firstly, during the dischargeperiod TD2, the sense amplifier enable signal ENSA and the dischargeenable signal DISEN are enable (be pulled to logic high), and thevoltage level VSA on the sensing end SE is pulled to the referenceground (ex. 0V). Then, during the pre-charge period TP2, the voltagelevel VSA on the sensing end SE is pulled to the preset voltage levelVPRE. It should be noted here, the voltage level VSA on the sensing endSE is prevented from rising over the trigger voltage level VTRIG by theovershoot prevention circuit 331, and the latched output signal LATOUTwith logic low can be obtained when the inverted latch enable signalZENLAT is pulled to logic low during the timing period TA2. After thepre-charge period TP2, the voltage level VSA is pulled down to thereference ground GND by comparing the reference current IREF and thecell current ICELL.

In additional, a memory cell which is programmed to a first logic level(“0” for example) has a larger cell current ICELL than a memory cellwhich is programmed to a second logic level (“1” for example) or erased.And the first logic level and the second logic level are complementary.

Referring to FIG. 5, FIG. 5 is a flow chart of a data sensing methodaccording to an embodiment of the present invention. In step S510, avoltage level on a sensing end is discharged to a reference groundduring a discharge period by an initial circuit. In step S520, thevoltage level on the sensing end is pre-charged to a preset voltagelevel during a pre-charge period according to an output signal by theinitial circuit. Further, in step S530, a cell current from the memorycell is received by the sensing end, and a reference current is drewfrom the sensing end by a reference current generator. Finally, in stepS540, the output signal is generated by sensing the voltage level on thesensing end by a sensing circuit.

The details of the steps S510-S540 can be realized by the description ofthe embodiments mentioned above.

In summary, the sensing apparatus of present invention provides aninitial circuit for pre-charging the voltage level of the sensing end toa preset voltage level. That is, a response time for sensing data by thesensing apparatus can be reduced, and a performance of the memory can beimproved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of theinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the invention covermodifications and variations of this invention provided they fall withinthe scope of the following claims and their equivalents

What is claimed is:
 1. A sensing apparatus, comprising: an initialcircuit, coupled to a sensing end, the initial circuit discharging thesensing end to a reference ground during a discharge period, andpre-charging the sensing end to a preset voltage level during apre-charge period according to an output signal; a reference currentgenerator, coupled to the sensing end and drawing a reference currentfrom the sensing end; and a sensing circuit, coupled to the sensing endfor sensing a voltage level on the sensing end to generate the outputsignal by sensing whether the voltage level on the sensing end is largerthan a trigger voltage level or not, wherein, the trigger voltage levelis larger than the preset voltage level, wherein, the sensing endreceives a cell current from a memory cell, and the pre-charge period isafter the discharge period, wherein the sensing circuit comprises: afirst transistor, has a first end, a second end and a control end, thefirst end of the first transistor is coupled to a reference operatingvoltage, the control end of the first transistor is coupled to thesensing end; and a current generator, coupled between the second end ofthe first transistor and the reference ground, the current generatorprovides a current flowing from the second end of the first transistorto the reference ground, wherein the current generator comprises: asecond transistor, has a first end, a second end and a control end, thefirst end of the second transistor is coupled to a output end of thesensing circuit, the control end of the second transistor receives abias voltage; and a third transistor, has a first end, a second end anda control end, the first end of the third transistor is coupled to thesecond end of the second transistor, the control end of the thirdtransistor receives a sense amplifier enable signal, and the second endof the third transistor is coupled to the reference ground.
 2. Thesensing apparatus according to claim 1, wherein the sensing circuitfurther comprises: an overshoot prevention circuit, coupled to theoutput end of the sensing circuit for generating the output signal, theovershoot prevent circuit draws a current from the output end of thesensing circuit during the pre-charge period.
 3. The sensing apparatusaccording to claim 2, wherein the overshoot prevention circuitcomprises: a fourth transistor, has a first end, a second end, and acontrol end, the first end of the fourth transistor is coupled to theoutput end of the sensing circuit, the control end of the fourthtransistor receives the bias voltage; and a fifth transistor, has afirst end, a second end, and a control end, the first end of the fifthtransistor is coupled to the second end of the fourth transistor, thecontrol end of the fifth transistor receives a pre-charge enable signal,and the second end of the fifth transistor is coupled to the referenceground.
 4. The sensing apparatus according to claim 1, wherein theinitial circuit comprises: a pre-charge circuit, coupled to the sensingend, and the pre-charge circuit pre-charges the sensing end to a presetvoltage level during the pre-charge period; and a discharge circuit,coupled to the sensing end, and the discharge circuit discharges thesensing end to a reference ground during the discharge period.
 5. Thesensing apparatus according to claim 4, wherein the pre-charge circuitcomprises: a sixth transistor, has a first end, a second end, and acontrol end, the first end of the sixth transistor is coupled to areference operating voltage, a control end of the sixth transistorreceives a pre-charge enable signal; and a seventh transistor, has afirst end, a second end, and a control end, the first end of the seventhtransistor is coupled to the second end of the sixth transistor, acontrol end of the seventh transistor receives the output signal, andthe second end of the seventh transistor is coupled to the sensing end.6. The sensing apparatus according to claim 4, wherein the pre-chargecircuit comprises: a current source, coupled to a reference operatingvoltage and generates a reference current; a switch, has a first end anda second end, the first end of the switch is coupled to the currentsource, wherein the switch receives a pre-charge enable signal and isturned on or off according to the pre-charge enable signal; and a sixthtransistor, has a first end, a second end, and a control end, the firstend of the sixth transistor is coupled to the second end of the switch,a control end of the sixth transistor receives the output signal, andthe second end of the sixth transistor is coupled to the sensing end. 7.The sensing apparatus according to claim 5, wherein the dischargecircuit comprises: an eighth transistor, has a first end, a second end,and a control end, the first end of the eighth transistor is coupled tothe sensing end, the control end of the eighth transistor receives adischarge enable signal, and the second end of the eighth transistor iscoupled to the reference ground.
 8. The sensing apparatus according toclaim 1, wherein the reference current generator comprise: a ninthtransistor, has a first end, a second end, and a control end, the firstend of the ninth transistor is coupled to the sensing end, the controlend of the ninth transistor receives a reference voltage; and a tenthtransistor, has a first end, a second end, and a control end, the firstend of the tenth transistor is coupled to the second end of the ninthtransistor, the control end of the tenth transistor receives an invertedpre-charge enable signal, and the second end of the tenth transistor iscoupled to the reference ground.
 9. The sensing apparatus according toclaim 1, further comprising: a switch, coupled between the sensing endand the memory cell, the switch being controlled by a sensing apparatusenable signal.
 10. The sensing apparatus according to claim 9, whereinthe switch comprises: a transmission gate, has a first end, a secondend, a positive control end and a negative control end, the first end iscoupled to the memory cell, the second end is coupled to the sensingend, the positive end receives the sense amplifier enable signal, andthe negative end receives an inverted sense amplifier enable signal. 11.The sensing apparatus according to claim 1, further comprising: a latchcircuit, coupled to the sensing circuit for receiving and latching theoutput signal.
 12. The sensing apparatus according to claim 11, whereinthe latch circuit comprises: a logical gate, receives the output signaland an inverted latch enable signal, and decides to transmit the outputsignal to an output end of the logical gate or not according to theinverted latch signal; and a latch gate, coupled to the output end ofthe logical gate, the latch gate latches the signal on the output end ofthe logical gate according to a latch signal.
 13. A data sensing method,suitable for sensing data from a memory cell, comprising: discharging avoltage level on a sensing end to a reference ground during a dischargeperiod by an initial circuit; pre-charging the voltage level on thesensing end to a preset voltage level during a pre-charge periodaccording to an output signal by the initial circuit; receiving a cellcurrent from the memory cell by the sensing end; drawing a referencecurrent from the sensing end by a reference current generator; drawing acurrent from an output end of the sensing circuit during the pre-chargeperiod by the sensing circuit; and generating the output signal bysensing the voltage level on the sensing end by a sensing circuit,wherein, the pre-charge period is after the discharge period.
 14. Thedata sensing method according to claim 13, wherein the steps of thegenerating the output signal by sensing the voltage level on the sensingend comprises: generating the output signal by sensing whether thevoltage level on the sensing end is larger than a trigger voltage levelor not, wherein, the trigger voltage level is larger than the presetvoltage level.
 15. The data sensing method according to claim 13,further comprising: latching the output signal according to a senseamplifier enable signal by a latch circuit.
 16. A sensing apparatus,comprising: an initial circuit, coupled to a sensing end, the initialcircuit discharging the sensing end to a reference ground during adischarge period, and pre-charging the sensing end to a preset voltagelevel during a pre-charge period according to an output signal; areference current generator, coupled to the sensing end and drawing areference current from the sensing end; and a sensing circuit, coupledto the sensing end for sensing a voltage level on the sensing end togenerate the output signal, wherein, the sensing end receives a cellcurrent from a memory cell, and the pre-charge period is after thedischarge period, wherein the reference current generator comprise: aninth transistor, has a first end, a second end, and a control end, thefirst end of the ninth transistor is coupled to the sensing end, thecontrol end of the ninth transistor receives a reference voltage; and atenth transistor, has a first end, a second end, and a control end, thefirst end of the tenth transistor is coupled to the second end of theninth transistor, the control end of the tenth transistor receives aninverted pre-charge enable signal, and the second end of the tenthtransistor is coupled to the reference ground.